The typical method of framing detection in the prior art has been to embed framing information in one of the plurality of multiplexed data channels and then have the detector check each channel of information until it finds a set of data bits which uniquely indicate that they are framing bits. The channels are then synchronized using this information and any switching of channels or delaying is done subsequent thereto.
Such an approach can require the searching and attempted synchronization for each of the channels before finding the proper channel. One approach in attempting to speed up this process is to have three different frame detectors all operating simultaneously and whichever one finds the framing information overrides the information from the other detectors in rerouting and/or delaying the signals to obtain the proper time synchronous outputs.
Since only one channel in the referenced prior approach has the framing information, the timing of the various channels or the circular permutations of data can be easily and quickly determined. In other words, if the framing information is placed on channel A, it is immediately obvious that the next subsequent bit is a B channel bit and the next subsequent bit is a C channel bit.
The present invention places the framing information on all three channels and additionally inserts a channel identity code in the overhead data of the channel. Thus, when framing is accomplished, the identity is detected and if the channel happens to be channel C, the logic circuitry knows immediately that the next bit will be channel A. However, it is also apparent that the data bits A and B following are not time synchronous with the channel C data just detected but rather with the following channel C data. Thus, if the output data is to be time synchronous for use by a parallel data load, appropriate rerouting of the signals and delaying of one or more of the signals must be accomplished prior to outputting the data.
The circuitry for accomplishing the above provides the simplest type of channel data extraction from the multiplexed data along with simple logic circuitry for framing detection and switching or rerouting of the signals as compared to the prior art circuitry for accomplishing the same function at a much longer framing acquisition time.
It is thus an object of the present invention to provide an improved high speed approach to framing of digital data to be used in a multiplexed system and framing acquisition of the channels of that data at the receiving and demultiplexing end.